View AD9508-17_9056369.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1.65 ghz clock fanout buffer with output dividers and delay adjust data sheet ad9508 rev. g document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assum ed by analog devices for its use, nor for any infringements of patents o r other rights of third parties that may result from its use. specifica tions subject to change without notice. no license is granted by implication or otherwise under any patent or pat ent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 ? 2017 analog devices , inc. all rights reserved. technical support www.analog.com features 1. 65 ghz differential clock inputs/outputs 10 - bit programmable dividers, 1 to 1024, all integers up to 4 differential outputs or 8 cmos outputs pin strapping capability for hardwired programming at power - up <115 fs rms broadband random jitter (see figure 25 ) additive output jitter: 41 fs rms typical (12 khz to 20 mhz) excellent o utpu t- to - output isolation automatic synchronization of all outputs single 2.5 v/3.3 v power supply internal ldo (l ow drop - out ) voltage regulator for e nhanced power supply immunity phase offset select for output - to - output coarse delay adjust 3 programmable output logic levels, lvds, hstl, and cmos serial control port (spi/i 2 c) or pin - programmable mode space - saving 24 - lead lfcsp applications low jitter, low phase noise clock distribution clocking high speed adcs, dacs, ddss, ddcs, ducs, mxfes high performance wireless transceivers high performance instrumentation broadband infrastructure functional block dia gram figure 1. general description the ad9508 provides clock fanout capability in a design that emphasize s low jitter to maximize system performance. this device benefits application s like clocking data c onverters with demanding phase noise and low jitter requirements. there are four independent differential clock outputs, each with various type s of logic levels available. available logic types include lvds (1. 65 ghz), hstl (1. 65 ghz), and 1.8 v cmos (250 mhz). in 1.8 v cmos output mode, the differential output b ecomes two cmos single - ended signals. the cmos outputs are 1.8 v logic levels , regardless of the operating supply voltage. each output has a programmable divider that can be bypassed or be set to di vide by any integer up to 1024. in addition, th e ad9508 supports a coarse output phase adjustment between the outputs. the device can also be pin programmed for various fixed configurations at p ower - up without the need for spi or i 2 c programming. the ad9508 is available in a 24 - lead lfcsp and operates from a either a single 2.5 v or 3.3 v supply. the temperature range is ? 40c to + 85 c. div/ out0 out0 out1 out1 out2 out2 out3 out3 control interface spi/i 2 c/pins ad9508 clk sclk/scl/s0 sdio/sda/s1 sdo/s3 cs/s2 sync clk pin control div/ div/ div/ reset 11 161-001
ad9508 data sheet rev. g | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 electrical characteristics ............................................................. 4 power supply current and temperature conditions .............. 4 clock inputs and output dc specifications ............................ 5 output driver timing characteristics ...................................... 6 logic inputs ................................................................................... 7 serial port specifications ? spi mode ........................................ 7 serial port specifications ?i 2 c mode ........................................ 8 external resistor values for pin strapping mode ................... 9 clock output additive phase noise .......................................... 9 clock output additive time jitter ........................................... 10 absolute maximum ratings .......................................................... 11 thermal characteristics ............................................................ 11 esd caution ................................................................................ 11 pin configuration and function descriptions ........................... 12 typical performance characteristics ........................................... 14 test circuits ..................................................................................... 20 input/output termination recommendations ...................... 20 terminology .................................................................................... 21 theory of operation ...................................................................... 22 detailed block diagram ............................................................ 22 programming mode selection .................................................. 22 clock input .................................................................................. 23 clock outputs ............................................................................. 24 clock dividers ............................................................................ 24 phase delay control .................................................................. 24 reset modes ................................................................................ 25 power - down mode .................................................................... 25 output clock synchronization ................................................. 25 power supply ............................................................................... 25 thermally enhanced package mounting guidelines ............ 25 pin strapping to program on power - up ..................................... 26 serial control port ......................................................................... 27 spi/i 2 c port selection ................................................................ 27 spi serial port operation .......................................................... 27 i 2 c serial port operation .......................................................... 30 register map ................................................................................... 33 register map bit descriptions ...................................................... 34 serial port configuration (register 0x00) .............................. 34 silicon revision (register 0x0a to register 0x0d) ............... 34 chip level functions (register 0x12 to register 0x14) ........ 34 out0 functions (register 0x15 to register 0x1a) ............... 35 out1 functions (register 0x1b to register 0x20) ............... 36 out2 functions (register 0x21 to register 0x26) ................ 37 out3 functions (register 0x27 to register 0x2c) ............... 38 packaging and ordering information ......................................... 40 outline dimensions ................................................................... 40 ordering guide .......................................................................... 40
data sheet ad9508 rev. g | page 3 of 40 revision history 6/2017 ? rev. f to rev. g updated outline dimensions ........................................................ 40 changes to ordering guide ........................................................... 40 4/ 2015 ? rev. e to rev. f changes to clock outputs section ............................................... 24 changes to table 28 ........................................................................ 35 changes to table 30 ........................................................................ 36 changes to table 32 ........................................................................ 38 changes to table 34 ........................................................................ 39 11 / 2014 ? rev. d to rev. e changes to figure 1 .......................................................................... 1 moved revision history section ..................................................... 3 changes to table 12 ........................................................................ 12 changes to clock outputs section , clock dividers section , and phase delay control section ......................................................... 24 changed individual clock channel power - down section to individual clock divider power - down section ......................... 25 changes to individual clock divider power - down section an d output c lock synchronization section ........................................ 25 changes to pin strapping to program on power - up section and table 15 ............................................................................................. 26 cha nges to table 27 and table 28 ................................................. 35 changes to table 29 a nd table 30 ................................................. 36 cha nges to table 31 and table 32 ................................................. 37 changes to table 33 ........................................................................ 38 changes to table 34 ........................................................................ 39 9/ 2014 ? rev. c to rev. d changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 4 changes to figure 37 caption ; added figure 38; renumbered sequentially ...................................................................................... 19 changes to clock input section and table 14 ............................. 23 2/ 2014 ? rev. b to rev. c changes to table 14 ........................................................................ 22 10/2013 ? rev. a to rev. b change to figure 5 caption ........................................................... 13 change to figure 13 caption ......................................................... 14 change to figure 19 caption ......................................................... 15 change to individual clock channel power - down section .... 23 change to write section ................................................................ 27 changes to table 27 ........................................................................ 34 changes to table 29 ........................................................................ 35 changes to table 31 ........................................................................ 36 changes to table 33 ........................................................................ 37 4/ 2013 ? rev. 0 to rev. a changes to table 9 ............................................................................ 9 changes to figure 10 ...................................................................... 14 changes to figure 15 ...................................................................... 15 changes to figure 24 and figure 26 ............................................. 16 changes to figure 27, figure 29 to figure 32 .............................. 17 changes to figure 33 ...................................................................... 18 1/ 2013 ? rev ision 0: initial version
ad9508 data sheet rev. g | page 4 of 40 specifications electrical character istics typical values are given for v s = 3.3 v and 2.5 v and t a = 25c ; m inimum and maximum values are given over the full v dd = 3.3 v + 5% down to 2.5 v ? 5% and t a = ?40c to +85c variation ; and i nput slew rate > 1 v/ns, unless otherwise noted. power supply current and t emperature conditions table 1. parameter min typ max unit test conditions/comments s upply voltage 2.375 2.5 3.465 v use s upply v oltage setting (2.5 v or 3.3 v) and appropriate current consumption configura tion (see current consumption parameters in table 1) to calculate total power dissipation current consumption lvds configuration 165 1 82 ma input clock: 1500 mhz in differential mode , a ll lvds output drivers at 1500 mhz 1 22 13 4 ma input clock: 800 mhz in differential mode , a ll lvds output drivers at 2 00 mhz hstl configuration 194 213 ma input clock: 1500 mhz in differential mode , a ll hstl output drivers at 1500 mhz 131 144 ma input clock: 491.52 mhz in differential mode , all output drivers at 491.52 mhz 92 101 ma input clock: 122.88 mhz in differential mode , all output drivers at 122.88 mhz cmos configuration 141 185 ma input clock : 1500 mhz in d ifferential mode , a ll cmos output drivers at 250 mhz , 10 pf load 122 134 ma input clock : 800 mhz in d ifferential mode , a ll cmos outputs drivers at 200 mhz , 10 pf load 85 94 ma input clock : 100 mhz in d ifferential mode , a ll cmos outputs drivers at 100 mhz , 10 pf load full power -d own 6 10 ma temperature ambient temperature range, t a ?40 +25 +85 c junction temperature, t j 115 c junction temperatures above 115 c can degrade performance but no damage should occur, unless the absolute temperature is exceeded
data sheet ad9508 rev. g | page 5 of 40 clock inputs and out put dc specification s table 2 . parameter symbol min typ max unit test conditions /comments clock inputs differential mode input frequency 0 165 0 mhz differential input input sensitivity 360 2200 mv p-p as measured with a differential probe ; j itter performance improves with higher slew rates (greater voltage swing) input common - mode voltage v icm 0.95 1.05 1.15 v input pins are internally self biased , which enables ac coupling input voltage offset 30 mv dc -c oupled input common - mode range v cmr 0.58 1.6 7 v this is the allowable c ommon - mode voltage range when dc - coupled pulse width low 303 ps high 303 ps input resistance ( single - ended ) 5.0 7 9 k input capacitance c in 2 pf input bias current (each pin) 100 400 a full input swing cmos clock mode (single - ended ) 2.5 v or 3.3 v cmos only; f or 1.8 v cmos, use (ac - coupled) differential input mode input frequency 250 mhz input voltage high v ih vdd/2 + 0.15 v low v il vdd/2 ? 0.15 v input current high i inh 1 a low i inl ? 142 a input capacitance c in 2 pf lvds clock outputs termination = 100 differential (outx, outx ) output frequency 165 0 mhz output voltage differential v od 247 375 454 mv v oh ? v ol measurement across a differential pair at the default amplitude setting with output driver not toggling; see figure 6 for variation over frequency delta v od ?v od 50 mv this is the absolute value of the difference between v od when the normal output is high vs . when the complementary output is high offset voltage v os 1.125 1.18 1.375 v (v oh + v ol )/2 across a differential pair delta v os ?v os 50 mv this is the absolute value of the difference between v os when the normal output is high vs . when the complementary output is high short- circuit current i s a, i s b 13 .6 24 ma each pin (output shorted to gnd) lvds duty cycle 45 55 % up to 75 0 mhz input 39 61 % 750 mhz to 1500 mhz input 50.1 % 165 0 mhz input hstl clock outputs 100 across differential pair ; d efault amplitude setting output frequency 165 0 mhz differential output voltage v o 859 925 978 mv v oh ? v ol with output driver static common - mode output voltage v ocm 905 9 40 971 mv (v oh + v ol )/2 with output driver static hstl duty cycle 45 55 % up to 750 mhz input 40 60 % 750 mhz to 1500 mhz input 50.9 % 1650 mhz input
ad9508 data sheet rev. g | page 6 of 40 parameter symbol min typ max unit test conditions /comments cmos clock outputs single - ended; termination = open; outx and outx in phase output frequency 250 mhz with 10 pf load per output, see figure 14 for swing vs. frequency output voltage at 1 ma load high v oh 1.7 v low v ol 0.1 v at 10 ma load high v oh 1.2 v low v ol 0.6 v at 10 ma load (2 cmos mode) high v oh 1.45 v low v ol 0.35 v cmos duty cycle 45 55 % up to 250 mhz output driver timing characteristics table 3. parameter symbol min typ max unit test conditions /comments lvds outputs termination = 100 differential , 1 lvds output rise/fall time t r , t f 152 177 ps 20% to 80% measured differentially propagation delay, clock - to - lvds output t pd 1.56 2.01 2.43 ns temperature coefficient 2.8 ps/c output skew 1 all lvds outputs on the same part 48 ps across multiple parts 781 ps assumes same temp erature and supply ; t akes into account worst - case propagation delay delta due to worst - case process variation hstl outputs termination = 100 differential , 1 hstl output rise/fall time t r , t f 1 18 143 ps 20% to 80% measured differentially propagation delay, clock - to - hstl output t pd 1.59 2.05 2.5 ns temperature coefficient 2.9 ps/c output skew 1 all hstl outputs on the same part 59 ps across multiple parts 82 5 ps assumes same temp erature and supply ; t akes into account worst - case propagation delay delta due to worst - case process variation cmos outputs output rise/fall time t r, t f 1.18 1.4 5 ns 20% to 80%; c load = 10 pf propagation delay, clock - to - cmos output t pd 2.04 2.56 3.07 ns 10 pf load temperature coefficient 3.3 ps/c output skew 1 all cmos outputs on the same part 112 ps across multiple parts 965 ps assumes same temp erature and supply ; takes into a ccount worst - case propagation delay delta due to worst - case process variation
data sheet ad9508 rev. g | page 7 of 40 parameter symbol min typ max unit test conditions /comments output logic skew 1 cmos load = 10 pf and lvds load = 100 lvds output(s) and hstl output(s) 77 119 ps outputs on the same device ; a ssumes worst - case output combination lvds output(s) and cmos output(s) 497 700 ps outputs on the same device; assumes worst - case output combination hstl output(s) and cmos output(s) 424 622 ps outputs on the same device; assumes worst - case output combination 1 output skew is the difference between any two similar delay paths whil e operating at the same voltage and temp erature. logic inputs table 4 . parameter symbol min typ max unit test conditions/comments logic inputs reset , sync , in_sel input voltage high v ih 1.7 v 2.5 v supply voltage operation 2.0 v 3.3 v supply voltage operation low v il 0.7 v 2.5 v supply voltage operation 0.8 v 3.3 v supply voltage operation input current i inh , i inl ?300 +100 a input capacitance c in 2 pf serial port specific ations ? spi mode table 5. parameter min typ max unit test conditions/comments cs sclk has a 200 k internal pull - down resistor input voltage logic 1 vdd ? 0.4 v logic 0 0.4 v input current logic 1 ?4 a logic 0 ? 85 a input capacitance 2 a sclk input voltage logic 1 vdd ? 0.4 v logic 0 0.4 v input current logic 1 70 a logic 0 13 a input capacitance 2 pf sdio as input input voltage logic 1 vdd ? 0.4 v logic 0 0.4 v input current logic 1 ?1 a logic 0 ?1 a input capacitance 2 pf
ad9508 data sheet rev. g | page 8 of 40 parameter min typ max unit test conditions/comments as output output voltage logic 1 vdd ? 0.4 v 1 ma load current logic 0 0.4 v 1 ma load current sdo output voltage logic 1 vdd ? 0.4 v 1 ma load current logic 0 0.4 v 1 ma load current timing sclk clock rate, 1/t clk 30 mhz pulse width high, t high 4. 6 ns pulse width low, t low 3.5 ns sdio to sclk setup, t ds 2.9 ns sclk to sdio hold, t dh 0 ns sclk to valid sdio and sdo, t dv 15 ns cs t o sclk setup (t s ) 3.4 ns cs to sclk hold (t c ) 0 ns cs to minimum pulse width high 3.4 ns serial port specifications ?i 2 c mode table 6. parameter min typ max unit test conditions/comments sda, scl (as input) input voltage logic 1 vdd ? 0.4 v logic 0 0. 4 v input current ?40 0 a for v in = 10% to 90% dvdd3 hysteresis of schmitt trigger inputs 150 mv sda (as output) output logic 0 voltage 0.4 v i o = 3 ma output fall time from v ih (min) to v il (max) 250 ns 10 pf c b 400 pf timing scl clock rate 400 khz bus - free time between a stop and start condition , t buf 1.3 s repeated start condition setup time , t su; sta 0.6 s repeated hold time start condition, t hd; sta 0.6 s after this period, the first clock pulse is generated stop condition setup time, t su; sto 0.6 s low period of the scl clock, t low 1.3 s high period of the scl clock, t high 0.6 s data setup time, t su; dat 100 ns data hold time, t hd; dat 0 0.9 s
data sheet ad9508 rev. g | page 9 of 40 external resistor values for pin s trapping mode table 7. parameter resistor polarity min typ max unit test conditions/comments external resistors using 10% tolerance resistor voltage level 0 pull d own to ground 820 voltage level 1 pull d own to ground 1.8 k voltage level 2 pull d own to ground 3.9 k voltage level 3 pull d own to ground 8.2 k voltage level 4 pull up to vdd 820 voltage level 5 pull up to vdd 1.8 k voltage level 6 pull up to vdd 3.9 k voltage level 7 pull up to vdd 8.2 k clock output additiv e phase noise table 8. parameter min typ max unit test conditions/comments clk - to - hstl or lvds additive phase noise clk = 1474.56 mhz, out x = 1474.56 mhz input slew rate > 1 v/ns divide ratio = 1 at 10 hz offset ? 88 dbc/hz at 100 hz offset ? 100 dbc/hz at 1 khz offset ? 109 dbc/hz at 10 khz offset ? 116 dbc/hz at 100 khz offset ? 135 dbc/hz at 1 mhz offset ?144 dbc/hz at 10 mhz offset ?14 8 dbc/hz at 100 mhz offset ?149 dbc/hz clk - to - hstl or lvds or cmos additive phase noise clk = 625 mhz, out x = 125 mhz input slew rate > 1 v/ns divide ratio = 5 at 10 hz offset ?114 dbc/hz at 100 hz offset ?125 dbc/hz at 1 khz offset ?133 dbc/hz at 10 khz offset ?141 dbc/hz at 100 khz offset ?159 dbc/hz at 1 mhz offset ?162 dbc/hz at 10 mhz offset ?163 dbc/hz at 20 mhz offset ?163 dbc/hz clk - to - hstl or lvds additive phase noise clk = 491.52 mhz, out x = 491.52 mhz input slew rate > 1 v/ns divide ratio = 1 at 10 hz offset ?100 dbc/hz at 100 hz offset ?111 dbc/hz at 1 khz offset ?120 dbc/hz at 10 khz offset ?127 dbc/hz at 100 khz offset ?146 dbc/hz at 1 mhz offset ?153 dbc/hz at 10 mhz offset ?153 dbc/hz at 20 mhz offset ?153 dbc/hz
ad9508 data sheet rev. g | page 10 of 40 clock output additiv e time jitter table 9. parameter min typ max unit test conditions/comments lvds output additive time jitter clk = 622.08 mhz, outputs = 622.08 mhz 41 fs rms bw = 12 khz to 20 mhz 70 fs rms bw = 20 khz to 80 mhz 69 fs rms bw = 50 khz to 80 mhz clk = 622.08 mhz, outputs = 155.52 mhz 93 fs rms bw = 12 khz to 20 mhz 144 fs rms bw = 20 khz to 80 mhz 142 fs rms bw = 50 khz to 80 mhz clk = 125 mhz , outputs = 125 mhz 105 fs rms bw = 12 khz to 20 mhz 2 09 fs rms bw = 20 khz to 80 mhz 2 06 fs rms bw = 50 khz to 80 mhz clk = 400 mhz , outputs = 50 mhz 184 fs rms bw = 12 k hz to 20 mhz hstl output additive time jitter clk = 622.08 mhz , output s = 622.08 mhz 41 fs rms bw = 12 khz to 20 mhz 56 fs rms bw = 100 hz to 20 mhz 72 fs rms bw = 20 khz to 80 mhz 70 fs rms bw = 50 khz to 80 mhz clk = 622.08 mhz , outputs = 155.52 mhz 76 fs rms bw = 12 khz to 20 mhz 87 fs rms bw = 100 hz to 20 mhz 158 fs rms bw = 20 khz to 80 mhz 156 fs rms bw = 50 khz to 80 mhz cmos output additive time jitter clk = 100 mhz , outputs = 100 mhz 91 fs rms bw = 12 khz to 20 mhz
data sheet ad9508 rev. g | page 11 of 40 absolute maximum rat ings table 10 . parameter rating supply voltage (vdd) 3.6 v maximum digital input voltage ?0.5 v to vdd + 0.5 v clk and clk ?0.5 v to vdd + 0.5 v maximum digital output voltage ?0.5 v to vdd + 0.5 v storage temperature range ?65c to +150c operating temperature range ?40c to +85c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditio ns for extended periods may affect product reliability. the following equation determines the junction temperature on the application pcb: t j = t case + ( jt p d ) where: t j is the junction temperature (c). t case is the case temperature (c) measured by the customer at the top center of the package. jt is the value as indicated in table 11 . p d is the power dissipation. value s of ja are provided for package comparison and pcb design considerations. ja can be used for a first - order approxi - mation of t j by the following equation: t j = t a + ( ja p d ) where t a is the ambient temperature (c). value s of jc are provided for package comparison and pcb design considerations when an external heat sink is required. value s of jb are provided for package comparison and pcb design considerations. thermal characterist ics thermal characteristics established using je dec51 - 7 and jedec51 - 5 2s2p test boards. table 11 . thermal characteristics, 24 - lead lfcsp symbol thermal characteristic (jedec 51 - 7 and jedec51 - 5 2s2p test boards 1 ) value 2 unit ja junctio n- to - ambient thermal resistance per jedec jesd51 - 2 (still air) 43.5 c/w jma junction - to - ambient thermal resistance, 1.0 m/sec airflow per jedec jesd51 - 6 (moving air) 40 c/w jma junction - to - ambient thermal resistance, 2.5 m/sec airflow per jedec jesd51 - 6 (moving air) 38.5 c/w jb junction - to - board thermal resistance per jedec jesd51 - 8 (still air) 16.2 c/w jc junction - to - case thermal resistance (die - to - heat sink) per mil - std - 883, method 1012.1 7.1 c/w jt junction - to - top - of - package characterization parameter per jedec jesd51 -2 (still air) 0.33 c/w 1 the exposed pad on the bottom of the package must be soldered to ground (vss) to achieve the specified thermal performance. 2 results are from simulations. the pcb is a jedec multilayer type. th ermal performance for actual applications requires careful inspection o f the conditions in the application to determine if they are similar to thos e assumed in these calculations. esd ca ution
ad9508 data sheet rev. g | page 12 of 40 pin configuration and function descripti ons figure 2 . pin configuration table 12 . pin function descriptions pin no. mnemonic description 1 cs /s2 chip select/pin programming. multipurpose pin . this pin is c ontrolled by the prog_sel pin. chip select ( cs ) is an active logic l ow cmos input used in the spi operation mode. when programming a device via spi mode , cs must be held low. in systems where more than one ad9508 is present, this pin enables individual programming of each ad9508 . in pin programming mode, this pin becomes s2 . in this mode, s2 is hard wired with a resistor to either vdd or ground. the resistor value and resistor biasing determine the output divider value for the outputs on pin 11 and pin 12 . see the pin strapping to program on power - up section for more details. 2 out0 lvds/hstl differential o utput or single - ended cmos o utput. 3 out0 complementary lvds/hstl differential output or single - ended cmos o utput. 4 sdo/s3 serial data output/pin programming. multipurpose pin . this pin is controlled by the prog_sel pin . sdo is configured as an output to read back the internal register settings in spi mode operation. i n pin programming mode, this pin becomes s3 , which is hard wired with a resistor to either vdd or ground. the resistor value and resistor biasing determine the output divider value for the outputs on p in 16 and pin 17. see the pin strapping to program on power - up section for more details. 5 ext_cap0 node for external decoupling capacitor for ldo . t ie t his pin to a 0.47 f capacitor to ground. 6 vdd power supply (2.5 v or 3.3 v o peration). 7 out1 lvds/hstl differential o utput or single - ended cmos o utput. 8 out1 complementary lvds/hstl d ifferential o utput or single - ended cmos o utput. 9 s4 pin programming. use t his pin in pin programming mode only. t he prog_sel pin determines which programming mode is used . in pin programming mode, s4 is hardwired with a resistor to either vdd or ground. the resistor value and resistor biasing determine the output logic levels used for the outputs on pin 2, pin 3, pin 7, and pin 8. see the pin strapping to program on power - up section for more details. 10 s5 pin programming. use this pin in pin programming mode only . t he prog_sel pin determines which programming mode is used . in pin programming mode, s 5 is hardwired with a resistor to either vdd or ground. the resistor value and resistor bias ing determine the output logic lev els used for the outputs on pin 11, pin 12, pin 16 , and pin 17. see the pin strapping to program on power - up section for more details. 11 out2 lvds/hstl differential o utput or single - ended cmos o utput. 12 out2 complementary lvds/hstl differential output or single - ended cmos o utput. 13 vdd power supply (2.5 v or 3.3 v o peration). 14 ext_cap1 node for external decoupling capacitor for ldo . t ie t his pin to a 0.47 f capacitor to ground. 15 prog_sel three -s tate cmos i nput. pin 15 s elects the type of device programming interface to be used (spi, i 2 c, or pin program ming ). 16 out3 lvds/hstl differential o utput or single - ended cmos o utput. 17 out3 complementary lvds/hstl differential o utput or single - ended cmos o utput. 2 1 3 4 5 6 18 17 16 15 14 13 vdd ext_cap0 sdo/s3 out0 out0 cs/s2 vdd notes 1. the exposed die pad must be connected to ground (vss). ext_cap1 prog_se l out3 out3 reset 8 9 10 11 7 out1 s4 s5 out2 12 out2 out1 20 19 21 sync sclk/scl/s0 clk 22 clk 23 in_se l 24 sdio/sda/s1 ad9508 top view 11 161-002
data sheet ad9508 rev. g | page 13 of 40 pin no. mnemonic description 18 reset cmos i nput. device reset. when this active low pin is asserted, the internal register sett ing s enter their default state after the reset is released. n ote that reset also serves as a power - down of the device while an active low signal is applied to the pin . the reset pin has an internal 24 k pull - up resistor. 19 sclk /scl/s0 serial programming clock/data clock/programming pin. multipurpose pin c ontrolled by the prog_sel p in u sed for serial programming clock (sclk) in spi m ode or data clock (scl) for serial programming i n i 2 c mode . the prog_sel pin determines which programming mode is used. in pin program ming mode, this pin becomes s0. in this mode, s0 is hardwired with a resistor to eit her vdd or ground. the resistor value and resistor biasing determine the output divider value s for the outputs on pin 2 and pin 3. see the pin strapping to program on power - up section for more details. 20 sync clock synchronization . when this pin is active low , the output drivers are held static and then synchronized on a low - to - high transition of this pin. the sync pin has an internal 24 k pull - up resistor. 21 clk differential c lock input or s ingle -e nded cmos i nput . whether this pin serves as the differential clock input or the single - ended cmos input depend s on the logic state of the in_sel pin. 22 clk complementary differential clock input . 23 in_sel cmos i nput. a logic high configures the clk and clk inputs for a differe ntial input signal. a logic low configures the input for single - ended cmos applied to the clk pin. ac - couple t he unused clk to ground with a 0.1 f capacitor. 24 sdio/sda/s1 seri al data input and output (spi)/ serial data (i 2 c)/pin programming. pin 24 is a m ultipurp ose i nput controlled by the prog_sel pin used for spi (sdio) , i 2 c (sda) , and pin strapping mode s (s1) . when the device is in 4 - wire spi mode, data is written via sdio. in 3 - wire mode, both data reads and writes occur on this pin. there is no internal pull - up/pull - down resistor on this pin. in i 2 c mode, sda serves as the serial data pin. the prog_sel pin de termines which programming mode is used. in pin programming mode, this pin becomes s1. in this mode, s1 is hardwired with a resistor to eit her vdd or ground. the resistor value and resistor biasing determine the output divider values for the outputs on pin 7 and pin 8. see the pin strapping to program on power - up section for more details. ep exposed pad. the exposed die pad must be connected to ground (vss).
ad9508 data sheet rev. g | page 14 of 40 typical performance characteristics figure 3. lvds differential output waveform at 800 mhz figure 4. lvds differential output waveform at 156.25 mhz figure 5. power supply current vs. input frequency and number of outputs used, lvds figure 6. lvds differential output swing vs. frequency figure 7. lvds differential output swing vs. power supply voltage figure 8. lvds propagation delay vs. input differential voltage time (250ps/div) voltage (100mv/div) 11161-003 time (1.5ns/div) voltage (100mv/div) 11161-004 200 one output (ma) two outputs (ma) three outputs (ma) four outputs (ma) 150 100 0 50 current (ma) frequency (mhz) 0 400 800 1200 1600 11161-005 800 frequency (mhz) 100 300 900 700 500 1100 1300 1500 differenti a l output swing (mv p-p) 700600 500 400 11161-006 800 power supply (v) 2.3 2.5 3.1 2.9 2.7 3.3 3.5 differenti a l output swing (mv p-p) 780 760 740 720 700 11161-008 2.0 2.1 2.2 2.3 2.4 1.8 1.7 2.0 1.6 1.8 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1.9 propag a tion del a y (ns) input differential (v p-p) 11161-009
data sheet ad9508 rev. g | page 15 of 40 figure 9. lvds propagation delay vs. input common-mode voltage figure 10. lvds output duty cycle vs. output frequency figure 11. cmos output waveform at 200 mhz with 10 pf load figure 12. cmos output waveform at 50 mhz with 10 pf load figure 13. power supply current vs. in put frequency vs. number of outputs used, cmos figure 14. cmos output swing vs . frequency and resistive load common-mode voltage (mv) propag a tion del a y (ns) 2.0 1.8 1.6 1.4 2.6 2.4 2.2 300 500 700 900 1100 1300 1500 11161-010 55 frequency (mhz) 400 200 0 600 800 1000 1200 1400 1600 duty cycle (%) 6050 45 40 divider 1 divider 2 (frequency range normalized from 0hz to 800mhz) divider 3 (frequency range normalized from 0hz to 500mhz) 11161-011 time (1.25ns/div) voltage (300mv/div) 11161-012 time (5ns/div) voltage (300mv/div) 11161-013 current (ma) 25 50 75 100 125 25 50 75 100 125 150 175 200 225 250 frequency (mhz) one output (ma) two outputs (ma) three outputs (ma) four outputs (ma) five outputs (ma) six outputs (ma) seven outputs (ma) eight outputs (ma) 11161-014 0 1.4 1.5 1.6 1.7 1.8 1.9 50 100 150 200 250 output swing (v p-p) frequency (mhz) 300 ? load 500 ? load 750 ? load 1k ? load 11161-015
ad9508 data sheet rev. g | page 16 of 40 figure 15. cmos output swing vs. fr equency and temperature (10 pf load) figure 16. cmos output swing vs. frequency and capacitive load (2 pf, 5 pf, 10 pf, 20 pf) figure 17. hstl differential output waveform at 800 mhz figure 18. hstl differential output waveform at 156.25 mhz figure 19. power supply current vs. in put frequency and number of outputs used, hstl figure 20. hstl differential output swing vs. frequency 0 1.0 1.4 1.2 1.6 1.8 2.0 50 100 150 200 250 output swing (v p-p) frequency (mhz) 11161-016 C40c +25c +85c 0 1.1 1.3 1.5 1.7 1.9 50 100 150 200 250 frequency (mhz) output swing (v p-p) 2pf load 5pf load 10pf load 20pf load 11161-017 time (250ps/div) voltage (300mv/div) 11161-018 time (1.5ns/div) voltage (300mv/div) 11161-019 200 150 100 0 50 current (ma) frequency (mhz) 0 400 800 1200 1600 one output (ma) two outputs (ma) three outputs (ma) four outputs (ma) 11161-020 2.0 1.8 frequency (mhz) 100 300 900 700 500 1100 1300 1500 differenti a l output swing (mv p-p) 1.9 1.7 1.6 1.5 1.4 1.3 1.2 11161-007
data sheet ad9508 rev. g | page 17 of 40 figure 21. hstl differential output swing vs. power supply voltage figure 22. hstl propagation delay vs. input differential voltage figure 23. hstl propagation delay vs. input common-mode voltage figure 24. hstl output duty cycle vs. output frequency figure 25. additive br oadband jitter vs. input slew rate, lvds, hstl (calculated from snr of adc method) figure 26. absolute phase noise in hstl mode with clock input at 622.08 mhz and outputs = 622.08 mhz, 311.04 mhz, 155.52 mhz 2.0 power supply (v) 2.3 2.5 3.1 2.9 2.7 3.3 3.5 differenti a l output swing (mv p-p) 1.9 1.8 1.7 1.6 1.5 11161-021 11161-022 2.0 2.1 2.2 2.3 2.4 1.8 1.7 2.0 1.6 1.8 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1.9 propag a tion del a y (ns) input differential (v p-p) common-mode voltage (mv) propag a tion del a y (ns) 2.0 1.8 1.6 1.4 2.6 2.4 2.2 300 500 700 900 1100 1300 1500 11161-023 55 frequency (mhz) 400 200 0 600 800 1000 1200 1400 1600 duty cycle (%) 6050 45 40 11161-024 divider 1 divider 2 (frequency range normalized from 0hz to 800mhz) divider 3 (frequency range normalized from 0hz to 500mhz) 80 90 100 110 120 130 140 150 024681 0 jitte r (f s rms) slew rate (v/ns) 11161-227 C170 C160 C150 C140 C130 C120 C110 C100 C90 C 80 10 100 1k 10k 100k 10m 100m 1m phase noise (dbc/hz) frequency offset (hz) hstl 155.52mhz hstl 311.04mhz hstl 622.08mhz 11161-228
ad9508 data sheet rev. g | page 18 of 40 figure 27 . absolute phase noise in lvds mode with clock input at 622.08 mhz and outputs = 622.08 mhz, 311.04 mhz, 155.52 mhz figure 28 . absolute phase noise of clock source at 622.08 mhz figure 29 . additive phase noise with clock input = 1474.56 mhz with hstl outputs = 1474.76 mhz figure 30 . additive phase noise with clock input = 1500 mhz with hstl outputs = 100 mhz figure 31 . additive phase noise with clock input = 622.08 mhz with hstl outputs = 155.52 mhz figure 32 . additive phase noise with clock input = 622.08 mhz with lvds outputs = 622.08 mhz C160 C150 C140 C130 C120 C110 C100 C90 C80 phase noise (dbc/hz) lvds 155.52mhz lvds 311.04mhz lvds 622.08mhz 11161-229 10 100 1k 10k 100k 10m 100m 1m frequency offset (hz) C170 C160 C150 C140 C130 C120 C1 10 C100 C90 C80 1 1000 100000 10000000 phase noise (dbc/hz) frequenc y offset (mhz) 11 161-230 C170 C160 C150 C140 C130 C120 C110 C100 C90 C80 phase noise (dbc/hz) 11161-329 10 100 1k 10k 100k 10m 100m 1m frequency (hz) marker frequency 1. 10hz 2. 100hz 3. 1khz 4. 10khz 5. 100khz 6. 1mhz 7. 10mhz 8. 100mhz amplitude C89.57dbc/hz C100.45dbc/hz C109.97dbc/hz C116.93dbc/hz C135.33dbc/hz C144.39dbc/hz C148.66dbc/hz C149.78dbc/hz 2 3 4 5 6 7 8 1 C80C90 C100C110 C120 C130 C140 C150 C160 C170 10 100 1k 10k 100k 1m 10m 100m marker frequency 1. 10hz 2. 100hz 3. 1khz 4. 10khz 5. 100.5khz 6. 1mhz 7. 10mhz amplitude C116.04dbc/hz C126.68dbc/hz C135.27dbc/hz C142.56dbc/hz C159.42dbc/hz C161.97dbc/hz C164.55dbc/hz 2 3 4 5 6 7 1 frequency (hz) phase noise (dbc/hz) 11161-330 C80C90 C100C110 C120 C130 C140 C150 C160 C170 10 100 1k 10k 100k 1m 10m 100m marker frequency 1. 10hz 2. 100hz 3. 1khz 4. 10khz 5. 100.5khz 6. 1mhz 7. 10mhz 8. 20mhz amplitude C112.35dbc/hz C118.81dbc/hz C127.84dbc/hz C135.97dbc/hz C151.91dbc/hz C157.87dbc/hz C159.78dbc/hz C157.88dbc/hz frequency (hz) phase noise ( dbc/hz) 11161-129 2 3 4 5 6 7 8 1 C80C90 C100C110 C120 C130 C140 C150 C160 C170 10 100 1k 10k 100k 1m 10m 100m marker frequency 1. 10hz 2. 100hz 3. 1khz 4. 10khz 5. 100.5khz 6. 1mhz 7. 10mhz 8. 20mhz amplitude C100.17dbc/hz C109.18dbc/hz C117.67dbc/hz C124.94dbc/hz C143.83dbc/hz C151.64dbc/hz C153.81dbc/hz C152.87dbc/hz 2 3 4 5 6 7 8 1 frequency (hz) phase noise ( dbc/hz) 11161-130
data sheet ad9508 rev. g | page 19 of 40 figure 33 . additive phase noise with clock input = 100 mhz with cmos outputs = 100 mhz C80C90 C100C110 C120 C130 C140 C150 C160 C170 10 100 1k 10k 100k 1m 10m 100m marker frequency 1. 10hz 2. 100hz 3. 1khz 4. 10khz 5. 100.5khz 6. 1mhz 7. 10mhz 8. 20mhz amplitude C114.15dbc/hz C127.18dbc/hz C134.13dbc/hz C141.63dbc/hz C154.66dbc/hz C155.37dbc/hz C152.86dbc/hz C153.09dbc/hz 2 1 3 4 5 6 7 8 frequency (hz) phase noise ( dbc/hz) 11161-131
ad9508 data sheet rev. g | page 20 of 40 test circuits input/output termination recommendations figure 34. typical ac-coupled or dc-c oupled lvds or hstl configurations figure 35. typical ac-coupled or dc-coupled cml configurations figure 36. typical ac-coupled or dc-coupled lvpecl configurations figure 37. typical 2.5 v or 3.3 v cmos configurations for short trace lengths figure 38. 1.8 v cmos logic configuration for input clock using differential mode figure 39. ac-coupled lvds or hstl output driver (100 resistor can go on either side of decoupling capacitors placed as close as possible to the destination receiver) figure 40. dc-coupled lvds or hstl output driver figure 41. interfacing the hstl driver to a 3.3 v lvpecl input (this method incorporates impedance matching and dc biasing for bipolar lvpecl receivers. if the receiver is self-bia sed, the termination scheme shown in figure 39 is recommended.) 100 ? clk clk 100 ? clk clk 11161-132 ad9508 ad9508 clk clk clk clk v cc v cc 11161-133 ad9508 ad9508 clk clk 50 ? 50 ? v cc C 2v clk clk 50 ? 50 ? ad9508 ad9508 v cc C 2v 11161-134 clk clk ad9508 11161-135 0.1f logic 1 0.1f 1.8v cmos driver in_sel clk clk ad9508 11161-200 11161-136 downstream device with high impedance input and internal dc-bias 0.1f 0.1f 100 ? ad9508 hstl or lvds 11161-137 ad9508 hstl or lvds z 0 = 50 ? z 0 = 50 ? single-ended (not coupled) lvds or 1.8v hstl high-impedance differential receiver 100 ? 11161-138 3.3v lvpecl 0.1f 0.1f ad9508 1.8v hstl z 0 = 50 ? z 0 = 50 ? single-ended (not coupled) 82 ? v s = 3.3 v 82 ? 127 ? 127 ?
data sheet ad9508 rev. g | page 21 of 40 terminology phase jitter and phase noise an ideal sine wave can be thought of as having a continuous and an even progression phase with time from 0 degrees to 360 degrees for each cycle. actual signals, however, display a certain amount of variation from ideal phase progression over time. this phenomenon is phase jitter. although many causes can contribute to ph ase jitter, one major cause is random noise, characterized statistically as being gaussian (normal) in distribution. phase jitter leads to a spreading out of the energy of the sine w ave in the frequency domain, pr oducing a continuous power spec trum. this power spectrum is usually reported as a series of values whose units are dbc/hz at a given offset in frequency from the sine wave (carrier). the value is a ratio (expressed in db) of the power contained within a 1 hz bandwidth with respect to the power at the carrier frequency. for each measurement, the offset from the carrier frequency is also given. it is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 khz to 10 mhz). this is called the integr ated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise contained within that offset freque ncy interval. phase noise has a detrimental effect on the performance of adcs, dacs, and rf mixers. it lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. time jitter phase noise is a frequency domain phenomenon. in the time domain, the same effect is exhibited as with time jitter. when observing a sine wave, the time of successive zero crossings varies. in a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. in both cases, the variations in timing from the ideal are the time jitter. because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or one sigma of the gaussian distribution. time jitter that occurs on a sampling clock for a dac or an adc decreases the snr and dynamic range of the converter. a sampling clock with the lowest possible jitter provides the highest performance from a given converter. a dditive phase noise additive phase noise is the amount of phase noise that is attributable only to the device or subsystem being measured. the residual phase noise system makes use of two devices operating in perfect quadrature. the correlated noise of any external components common to both devices (such as clock sources) is not present. this makes it possible to predict the degree to which the device is going to affec t the total system phase noise when used in conjunction with t he various oscillators and clock sources, each of which contribute their own phase noise to the total. in many cases, the phase noise of one element dominates the system phase noise. additive time jitter additive time jitter refers to the amount of time ji tter that is attributable to the device or subsystem being measured. it is calculated by integrating the additive phase noise over a specific range. this makes it possible to predict the degree to which the device is going to impact the total system time j itter when used in conjunction with the various oscillators and clock sources, each of which contribute their own time jitter to the total. in many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
ad9508 data sheet rev. g | page 22 of 40 theory of operation detailed block diagram figure 42. detailed block diagram the ad9508 accepts either a differential input clock applied to the clk and clk pins or a single-ended 1.8 v (if ac-coupled) 2.5 v or 3.3 v cmos clock applied to the clk pin. the input clock signal is sent to the clock distribution section, which ha s programmable dividers and phase offset adjustment. the clock distribution section operates at speeds of up to 1650 mhz. the divider range under spi or i 2 c control ranges from 1 to divide-by-1024 and the phase offset adjustment is equipped with 11 bits of resolution. however, in pin programming mode, the divider range is limited to a maximum divide-by-16 and there is no phase offset adjustment available. the outputs can be configured to as many as four lvds/hstl differential outputs or as many as eight 1.8 v cmos single-ended outputs. in addition, the output current for the different outputs is adjustable for output drive strength. the device can be powered with either a 3.3 v or 2.5 v external supply; however, the internal supply on the chip runs off an internal 1.8 v ldo, delivering high performance with minimal power consumption. programming mode selection the ad9508 supports both spi and i 2 c protocols, and a pin strapping option to program the device. the active interface depends on the logic state of the prog_sel pin. see table 13 for programming mode selections. see the serial control port and pin strapping to program on power-up sections for more detailed information. table 13. spi/i 2 c/pin serial port setup prog_sel spi/i 2 c/pin float spi logic 0 i 2 c logic 1 pin programming control digital logic and registers spi interface i 2 c interface 10-bit divider scl sda clk spi/i 2 c/pin_ prog coarse a/d pin program read control sync lvds/hstl/cmos outputs ldo sub ldo sub ldo vdd reset ldo revision id 11-bit ? 11-bit ? 11-bit ? 11-bit ? 10-bit divider 10-bit divider 10-bit divider clk in_sel prog_sel s clk/scl/s0 sdio/sda/s1 sdo/s3 s4s5 cs/s2 ext_cap0 out0 out0 out1 out1 out2 out2 out3 out3 ext_cap1 vdd 11161-139 6
data sheet ad9508 rev. g | page 23 of 40 clock i nput the in_sel pin controls the desired input clock configuration. when the in_sel pin is set for single - ended o peration, the device expects 1.8 v (if ac - coupled) , 2.5 v, or 3.3 v cmos - compatible logic lev els on the clk input pin. bypass t he unused clk pin to ground with a 0.1 f capacitor . not e that if 2.5 v cmos logic is used for single- ended input clock mode , the 2.5 v power supply option is recommended instead of 3.3 v operation to avoid possible duty cycle distortion . duty cycle distortion can occur when the switching threshold level (vdd/2 or 1.65 v for 3.3 v operation) is increased and slow rise and falls times exist at the clock input . 1.8 v cmos logic levels are not recommended in a single - ended cmos configuration due to v ih being too close to the input threshold voltage. however, the differential input clock mode can be used for a 1. 8 v cmos input, and figure 38 shows the recommended configuration for a 1.8 v cmos input clock. when the in_sel pin is set for differential input clock mode, the inpu ts of the ad9508 are i nternally self biased. the internal inputs have a resistor divider, which sets the common - mode level . the complementary input is biased about 30 mv lower than the true input to avoid oscillations in the event that the input signal ceases. see figure 43 for the equivalent differ ential input circuit. figure 43 . a d9508 differential input stage the inputs can be ac - coupled or dc - coupled in differential mode . see table 14 for input logic compatibility. the user can supply a single - ended input with the input in differential mode by ac or dc coupling to one side of the differential input and b ypass ing the other input to ground by a capacitor. note that jitter performance degrades with low input slew rate, as shown in figure 25 . see figure 34 through figure 37 for different input clock termination schemes. table 14 . clk and clk differential input logic compatibility input logic type input common mode (v) input voltage swing (per leg) (v) ac - coupled dc - coupled 3.3 v cml 2.9 0.8 yes not allowed 2.5 v cml 2.1 0.8 yes not allowed 1.8 v cml 1.4 0.8 yes yes 3.3 v cmos 1 1.65 3.3 not allowed yes 2.5 v cmos 1, 2 1.25 2.5 not allowed yes 1.8 v cmos 3 0.9 1.8 yes not recommended 1.5 v hstl 0.75 0.75 yes yes lvds 1.25 0.4 yes yes 3.3 v lvpecl 2.0 0.8 yes not allowed 2.5 v lvpecl 1.2 0.8 yes yes 1 in_sel is set for single - ended cmos mode. 2 vdd = 2.5 v operation recommended vs . vdd = 3.3 v operation. 3 refer to figure 38 for configuration. 12.5k? 13k? 16.5k? 16k? v dd clk clk gnd 11 161-140
ad9508 data sheet rev. g | page 24 of 40 clock outputs each output driver can be configured for either a differential lvds/hstl output or two single - ended cmos outputs. when the lvds/hstl driver is enabled, the corresponding cmos driver is in tristate. when the cmos driver is enabled, the corresponding lvds/hs tl driver is powered down and tristated . see figure 44 and figure 45 for the equivalent output stages. figure 44 . lvds/hstl output simplified equivalent circuit figure 45 . cmos equivalent output circuit in lvds or hstl modes, there are register settings to contro l the output logic type and current drive strength. the lvds output current can be set to the nominal 3.5 ma, additional settings include 0.5, 0.75, 1.0 (default), and 1.25 multiplied by 3.5 ma. t he hstl output current can be set to 8 ma (nominal) or 16 ma (boost mode ). for pin programming mode, see the pin strapping to program on power - up section for details and limitations of the device. under pin programming mode, the nominal current is the default setting and is nonadjustable. when routing single - ended cmos signals, avoid driving multiple input receivers with one output. series termination at the source is generally required to provide transmission line matching and /or to reduce current transients at the driver. the value of the series resistor is dependent on the board design and timing requ irements (typically 10 to 100 ). cmos outputs are a lso limited in terms of the capacitive load or trace length that they can drive. typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and signal integrity. figure 46 . series termination of cmos outp ut clock dividers the four independent output divider s are 10 - bit integer dividers with a divide range of 1 to 1024 in spi and i 2 c modes. the output divider block contains duty cycle correction that guarantees 50 % duty cycle for both even and odd divide ratios. in pin programming mode , divide values of 1 to 8 and 16 are supported. p hase delay control the ad9508 provides a coarse output phase delay adjustment between output s but with a wid e delay ra nge that is beneficial for some applications . the minimum delay step is equivalent to half the period of the input clock rate. this minimum delay step can be multiplied from 1 to 2047 times the minimum delay step to cover a wide delay range. the multiplication of the minimum delay step is pr ovided for each output via the appropriate internal programming register . phase delay is not supported in pin programming mode. note that the phase delay adjustment requires the use of the syn c function pin. phase adjustment and output synchronization occurs on the rising edge of the sync pin . therefore, the sync pin must b e pulled low and released to produce the desired phase relationship between outputs . if the sync is not active low prior to a phase delay change, the desired output phase delay between outputs is not guaranteed to occur ; instead, a random phase delay can occur between outputs. however , a future sync pu lse correct s to the desired phase relationship , if initiated . during the active low sync period, the ou tputs are forced to a static state. figure 47 shows three independent output s , each set for div = 4 of the input clock rate . by incrementing the phase offset value in the programming registers from 0 to 2, each output is offset from the initial edge by a multiple of ? t clk . note that the sync signal is not shown in this timing diagram. figure 47 . phase offset ? all dividers set for div = 4, phase set from 0 to 2 outx outx v dd 11 161-141 outxa outxb 11 161-142 v dd v dd ad9508 cmos 10? 60.4? (1.0 inch) microstrip 11 161-143 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 clock input clk divider outputs div = 4, duty = 50% start = 0, phase = 0 start = 0, phase = 1 start = 0, phase = 2 t clk 11 161-144
data sheet ad9508 rev. g | page 25 of 40 reset modes the ad9508 has a power - on reset (por) and other ways to apply a reset condition to the chip. power - on reset during chip power - up, an internal power - on reset pulse is issued when vdd reaches ~1.15 v and restores the chip to the default on - chip setting. it takes ~20 ms for the outputs to begin toggling after the power - on reset pulse signal is internally generated. in spi or i 2 c modes, t he default power - on state of the ad9508 is configured as a buffer with th e dividers set to divide by 1. in p in programmable mode, the part is configured per the hardwiring of the s0 to s5 pins. hardware reset via the reset pin a hard asynchronous reset is executed by briefly pulling reset low. this restores the chip to the on - chip default register settings. it takes ~20 ms for the outputs to begin toggling after reset is released . soft reset via the serial port a soft reset is initiated by setting bit 2 and bit 5 in regis ter 0x000. except for register 0x000, w hen bit 5 and bit 2 are set, the chip enters a soft reset mode and restores the chip to the on - chip setting. these bits are self clearing. however, the self clearing operation does not complete until an additional ser ial port sclk cycle occurs, and the ad9508 is held in reset until that happens . power -d own mode individual clock divider power - down in spi or i 2 c programming mode, t he clock distribution dividers can be powered down individually by writing to the appropriate registers. powering down a clock divider is similar to powering down an individual driver, but it saves more power because additional circuits are also powered down. the register map details t he individual power - down settings for each output divider . the power - down bits for individual dividers are found in register 0x19, bit 7 ; register 0x1f , bit 7; register 0x25 , bit 7; and register 0x2b , bit 7. note that i n all three programming mode s, a logic low on the reset pin can be used to power down the device. output clock synchro nization on power u p, the default divider value isdivide - by -1 if spi and i 2 c programming modes are used . therefore , there is no re quirement for synchr onization after power up unless a change in divider value or a phase offset value is desired. the user can synchronize the outputs by pulling the sync pin low. the output drivers are static while the sync pin is low, and the outputs are edge aligned , regardless of their divide ratio after the sync pin releases . when t he sync mask bit is set to a l ogic 1, the associated output continue s working uninterrupted while applying a sync operation to other outputs . outputs are pulled low while sync is low if they are no t masked by the sync mask bit. this only applies if output s are functioning under normal operation with its l ogic level set to 11 or toggle mode. power supply the ad9508 is designed to work off a 3.3 v + 5% power supply down to a 2.5 v ? 5% power supply. best practice recommends bypassing the power supply on the printed circuit board ( pcb ) with adequate capacitance (>10 f) and bypassing all power pi ns with adequate capacitance (0.1 f) as close to the part as possible. the layout of the ad9508 evaluation board ( ad9508 /pcbz ), available at www.analog.com , provides a good layout example for this device . thermally enhanced p ackage mounting guidelines exposed metal paddle the exposed metal paddle on the ad9508 package is an electrical connection, as well as a thermal enhancement. for the device to function properly, the paddle must be properly attached to ground (v ss ). the ad9508 dissipates heat through its exposed paddle. the pcb acts as a heat sink for the ad9508 . the pcb attachment must provide a good thermal path to a larger heat dissipation area, such as the ground plane on the pcb. this requires a grid of vias from the top layer down to the ground plane. see figure 48 for an example. figure 48 . pcb land example for attaching exposed paddle refer to the an - 772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) , for more information about mounting devices with an exposed paddle. vias to gnd plane 11161-145
ad9508 data sheet rev. g | page 26 of 40 pin strapping t o program on power -up the prog_sel input when set to l ogic 1 places the ad9508 in pin strapp i ng control mode without the need fo r spi or i 2 c operation s . in this mode, pin s0 through pin s5 program the desired internal divider value and output logic t ype for each o utput or to set the output to a high - z state. in this mode, the max imum divide value is limited to divide - by - 16 and phase offset delay control is not supported. lvds and hstl logic types are support ed in this mode. however, if hstl mode is s et and the 100 output termination is removed , the output swing s to 1.8 v cmos logic levels . in this configuration , the differential pair of the selected output become two single - ended cmos signals. t hose outputs maintain a 180 phase relationship and share the same divide ratio. programming individual outputs and the output logic type is performed by hard wiring specific resistor values to each of the s0 to s5 pins. the other side of the resistor is then biased to ground or vdd , depen ding on the desired settings. the actual settings are applied after an internal adc scans each one of the s0 to s5 pins. an adc scan is initiated by either the internal power - on reset when the device is powered up or by toggling the sync pin . if changes are made after the internal power - on reset, the sync pin must be toggled before any new changes are accepted. table 15 d epicts all the pin strapping selections availa ble for each output divider value and logic type. the resistors listed in table 15 must have 10% or better tolerance . note that i f all outputs use a n output divide r value of one and use either hstl o utputs or 1.8 v cmos output levels, then the s0 to s5 pins can be grounded to accomplish that particula r configuration instead of using the 820 resistor. table 15 . selection table for pin strapping control program ming pins adc voltage level (0 through 7) vs. resistor value vs. divide value and log ic type output 0 = 820 pulled to gnd 1 = 1.8 k pulled to gnd 2 = 3.9 k pulled to gnd 3 = 8.2 k pulled to gnd 4 = 820 pulled to vdd 5 = 1.8 k pulled to vdd 6 = 3.9 k pulled to vdd 7 = 8.2 k pulled to vdd s0 out0 1 2 3 4 5 6 8 16 s1 out1 1 2 3 4 5 6 8 16 s2 out2 1 2 3 4 5 6 8 16 s3 out3 1 2 3 4 5 6 8 16 s4 out0 hstl lvds high -z hstl lvds high -z hstl high -z out1 hstl hstl hstl lvds lvds lvds high -z high -z s5 out2 hstl lvds high -z hstl lvds high -z hstl high -z out3 hstl hstl hstl lvds lvds lvds high -z high -z
data sheet ad9508 rev. g | page 27 of 40 serial control port the ad9508 serial control port is a flexible, synchronous serial communications port that provides a convenient interface to many industry - standard microcontrollers and microprocessors. the serial control port is compatible with most synchronous transfer formats, in cluding i 2 c, motorola spi, and intel ssr protocols. the serial control port allows read/write access to the ad9508 register map. in spi mode, single - or multiple - byte transfers are supported. the spi port configuration is programmable via register 0x0 0. this register is integrated into the spi control logic rather than in the register map and it is distinct from the i 2 c register 0x00. spi/i 2 c port selection the ad9508 has two serial interfaces, spi and i 2 c. users can select either spi or i 2 c depen ding on the state of the prog_sel pin. in i 2 c operation , four different i 2 c slave address (seven bits wide) settings are available , see table 16 . the five msbs of the slave address are hardware coded as 1 1 011 and pin s4 and pin s5 program the two lsbs. table 16 . serial port mod e selection s4 s5 address low low i 2 c, 1 1 01100 low high i 2 c, 1 1 0110 1 high low i 2 c, 1 1 011 10 high high i 2 c, 1 1 011 11 spi serial port operatio n pin descriptions the sclk (serial clock) pin serves as the serial shift clock. this pin is an input. sclk synchronizes serial control port read and write operations. the rising edge sclk registers write data bits, and the falling edge registers read data bits. the sclk pin supports a maximum clock rate of 40 mhz. the sdio (serial data input/output) pin is a du al - purpose pin and acts either as an input only (unidirectional mode) or as both an input and an output (bidirectional mode). the ad9508 default spi mode is bidirectional. the sdo (serial data output) pin is useful only in unidirectional i/o mode. it serves as the data output pin for read operations. the cs (chip select) pin is an active low control that gates read and write operations. this pin is internally connected to a 30 k pull - up resistor. w hen cs is high, the sdo and sdio pins enter a high impedance state. spi mode operation the spi port supports both 3 - wire (bidirectional) and 4 - wire (unidirectional) hardware configurations and both msb first and lsb first data formats. both the hardware configuration and data format features are programmable. by default, the ad9508 uses the bidirectional msb first mode. the reason that bidirectional is t he default mode is so that the user can continue to write to the device ( if it is wired for unidirectional operation ) to switch to unidirectional mode. assertion (active low) of the cs pin i nitiates a write or read operation to the ad9508 spi port. for data transfers of three bytes or fewer (excluding the instruction word), the device supports the cs stalled high mode. in this mode, the cs p in can be temporarily deasserted on any byte boundary, allowing time for the system controller to process the next byte. however, cs can be deasserted on byte boundaries only; t his applies to both the instruction and data portions of the transfer. during stall high periods, the serial control port state machine enters a wait state until all data is sent. if the system controller decides to abort a transfer midstream, the state machine must be reset either by completing the transfer or by a sserting the cs pin for at least one complete sclk cycle (but less than eight sclk cycles). deasserting the cs pin o n a nonbyte boundary terminates the serial transfer and flushes the buffer. in streaming mode (see table 17 ), any number of data bytes can be transferred in a continuous stream. the register address is automatically incremented or decremente d. cs must be deasserted at the end of t he last byte that is transferred, thereby ending the stream mode. table 17 . byte transfer count w1 w0 bytes to transfer 0 0 1 0 1 2 1 0 3 1 1 streaming mode communication cycle ? instruction plus data the spi protocol consists of a two part communication cycle. the first part is a 16 - bit instruction word that is coincident with the first 16 sclk rising edges and a payload. the instruction word provides the ad9508 serial control port with information regarding the payload. the instruction word includes the r/ w b it that indicates the dir ection of the payload transfer; tha t is, a read or write operation . the instruction word also indicates the numbe r of bytes in the payload and the starting register address of the first payload byte.
ad9508 data sheet rev. g | page 28 of 40 write when the instruction word indicates a write operation, the payload is written into the serial control port buffer of the ad9508 . data bits are registered on the rising edge of sclk. t he length of the transfer ( one , two , or three bytes or streaming mode) depends on the w0 and w1 bits in the instruction byte. when not s trea ming, cs can be deasserted after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle) . w hen the bus is stalled, the serial transfer resumes when cs is asserted. deasserti n g the cs pin on a nonbyte boundary resets the serial control port. reserved or blank registers are not skipped automatically during a write sequence. therefore, the user must know what bit pattern to write to the reserved registers to pr eserve proper operation of the device . generally, it does not matter what data is written t o blank registers, but it is customary to write 0s. read the ad9508 supports the long instruction mode only. if the instruction word indicates a read operation, the next n 8 sclk cycles clock out the data from the address specified in the instruction word. n is the number of data bytes read and depends on the w0 and w1 bits of the instruction word. the readback data is valid on the falling edge of sclk. blank regist ers are not skipped during readback. a readback operation takes data from either the serial control port buffer registers or the active registers . spi instr uction word (16 bits) the msb of the 16 - bit instruction wor d is r/ w , w hich indicates whether the instruction is a read or a write. the next two bits, w1 and w0, indicate the number of bytes in the transfer . the final 13 bits are the regis ter address (a12 to a0), which indicates the starting register address of the read/write operation (see table 19 ). spi msb first and lsb first transfers the ad9508 instruction word and payload can be msb first or lsb first ; t he default is msb first. the lsb first mode can be set by writing a 1 to register 0x 00, bit 6. immediately after the lsb first bit is set, subsequent serial control port operations are lsb first. when msb first mode is active, the instruction and data bytes must be written from msb to lsb. multibyte data transfers in msb first format start with an instruction byte that incl udes the r egister address of the most significant payload byte. subsequent data bytes must follow, in order, from high address to low address. in msb first mode, the serial control port internal address generator decrements for each data byte of the multibyte transf er cycle. when register 0x 00, bit 6 = 1 (lsb first), the instruction and data bytes must be written from lsb to msb. multibyte data transfers in lsb first format start with an instruction byte that includes the register address of the least significant pa yload byte, followed by multiple data bytes. the serial control port internal byte address generator increments for each byte of the multibyte transfer cycle. for multibyte msb first (default) i/o operations, the serial control port register address decrem ents from the specified starting address tow ard address 0x 00. for multibyte lsb first i/o operations, the serial control port register address increments from the sta rting address toward address 0x 2c . reserved addresses are not skipped during multibyte i/o operations; therefore, the user write s the de fault value to a reserved register and writes 0s to unmapped registers. note that it is more efficient to issue a new write command than to write the default value to more than two consecut ive reserved (or unmapped) registers. table 18 . streaming mode (no addresses skipped) write mode address direction stop sequence lsb first increment 0x00 ? 0x2c msb first decrement 0x2c ? 0x0 0 table 19 . serial control port, 16 - bit instruction word, msb first bit map msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/ w w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 figure 49 . serial control port write ? msb first, 16 - bit instruction, two bytes of data cs sclk don't care sdio a12 w0 w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care don't care 16-bit instruction header register (n) d at a register (n C 1) d at a 11 161-028
data sheet ad9508 rev. g | page 29 of 40 figure 50 . serial control port read ? msb first, 16 - bit instruction, four bytes of data figure 51 . serial control port write ? msb first, 16 - bit instruction, timing measurements figure 52 . timing diagram for serial control port register read figure 53 . serial control port write ? lsb first, 16 - bit ins truction, two bytes of data figure 54 . serial control port timing ? write cs sclk sdio sdo register (n) d at a 16-bit instruction header register (n C 1) d at a register (n C 2) d at a register (n C 3) d at a a12 w0w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 don't care don't care don't care don't care d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 11 161-029 t s don't care don't care w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 d4 d3 d2 d1 d0 don't care don't care r/w t ds t dh t high t low t clk t c cs sclk sdio 11 161-030 d at a bit n C 1 d at a bit n cs sclk sdio sdo t dv 11 161-031 cs sclk don't care don't care 16-bit instruction header register (n) d at a register (n + 1) d at a sdio don't care don't care a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d1 d0 r/w w1 w0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 11 161-032 cs sclk sdio t high t low t clk t s t ds t dh t c bit n bit n + 1 11 161-033
ad9508 data sheet rev. g | page 30 of 40 table 20. serial control port timing parameter description t ds setup time between data and the rising edge of sclk t dh hold time between data and the rising edge of sclk t clk period of the clock t s setup time between the cs falling edge and the sclk rising edge (start of the communication cycle) t c setup time between the sclk rising edge and cs rising edge (end of the communication cycle) t high minimum period that sclk should be in a logic high state t low minimum period that sclk should be in a logic low state t dv sclk to valid sdio and sdo (see figure 52) i 2 c serial port operation the i 2 c interface has the advantage of requiring only two control pins and is a de facto standard throughout the i 2 c industry. however, its disadvantage is the programming speed, which is 400 kbps maximum. the ad9508 i 2 c port design is based on the i 2 c fast mode standard; therefore, it supports both the 100 khz standard mode and 400 khz fast mode. fast mode imposes a glitch tolerance requirement on the control signals; that is, the input receivers ignore pulses of less than 50 ns duration. the ad9508 i 2 c port consists of a serial data line (sda) and a serial clock line (scl). in an i 2 c bus system, the ad9508 is connected to the serial bus (data bus sda and clock bus scl) as a slave device; that is, no clock is generated by the ad9508 . the ad9508 uses direct 16-bit memory addressing rather than traditional 8-bit memory addressing. the ad9508 allows up to four unique slave devices to occupy the i 2 c bus. these slave devices are accessed via a 7-bit slave address that is transmitted as part of an i 2 c packet. only the device that has a matching slave address responds to subsequent i 2 c commands. table 16 lists the supported device slave addresses. i 2 c bus characteristics table 21 provides a summary of the various i 2 c abbreviations used in the protocol. table 21. i 2 c bus abbreviation definitions abbreviation definition s start sr repeated start p stop ack acknowledge nack no acknowledge w write r read the transfer of data is shown in figure 55. one clock pulse is generated for each data bit transferred. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can change only when the clock signal on the scl line is low. figure 55. valid bit transfer start/stop functionality is shown in figure 56. the start condition is characterized by a high-to-low transition on the sda line while scl is high. the start condition is always generated by the master to initialize a data transfer. the stop condition is characterized by a low-to-high transition on the sda line while scl is high. the stop condition is always generated by the master to terminate a data transfer. every byte on the sda line must be eight bits long. each byte must be followed by an acknowledge bit; bytes are sent msb first. the acknowledge bit (ack) is the ninth bit attached to any 8-bit data byte. an acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received. the acknowledge bit is communicated by pulling the sda line low during the ninth clock pulse after each 8-bit data byte (see figure 57). the no acknowledge bit (nack) is the ninth bit attached to any 8-bit data byte. the receiving device (receiver) always generates the no acknowledge bit to inform the transmitter that the byte has not been received. the no acknowledge bit is communicated by leaving the sda line high during the ninth clock pulse after each 8-bit data byte. data line stable; data valid change of data allowed sda scl 11161-034
data sheet ad9508 rev. g | page 31 of 40 figure 56. start and stop conditions figure 57. acknowledge bit data transfer process the master initiates a data transfer by asserting a start condition, which indicates that a data stream follows. all i 2 c slave devices connected to the serial bus respond to the start condition. the master then sends an 8-bit address byte over the sda line, consisting of a 7-bit slave address (msb first) plus an r/ w bit. this bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). the peripheral whose address corresponds to the transmitted address responds by sending an acknowledge bit. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is 0, the master (transmitter) writes to the slave device (receiver). if the r/ w bit is 1, the master (receiver) reads from the slave device (transmitter). the format for these commands is described in the data transfer format section. data is then sent over the serial bus in the format of nine clock pulses: one data byte (eight bits) from either master (write mode) or slave (read mode) followed by an acknowledge bit from the receiving device. the number of bytes that can be transmitted per transfer is unrestricted. in write mode, the first two data bytes immediately after the slave address byte serve as the internal memory (control registers) address bytes, with the high address byte first. this addressing scheme gives a memory address of up to 2 16 ? 1 = 65,535. the data bytes after these two memory address bytes are register data that are written to or read from the control regist ers. in read mode, the data bytes after the slave address byte are register data that are written to or read from the control registers. when all data bytes are read or written, stop conditions are established. in write mode, the master (transmitter) asserts a stop condition to end data transfer during the 10 th clock pulse following the acknowledge bit for the last data byte from the slave device (receiver). in read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but does not pull sda low during the ninth clock pulse. this condition is known as a no acknowledge bit. by receiving the no acknowledge bit, the slave device knows that the data transfer is finished and enters idle mode. the master then takes the data line low during the low period before the 10 th clock pulse and high during the 10 th clock pulse to assert a stop condition. a start condition can be used in place of a stop condition. furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded. figure 58. data transfer process (master write mode, two-byte transfer) sda start condition stop condition scl s p 11161-035 12 89 12 3to 7 3to 7 89 10 sda scl s msb ack from slave receiver ack from slave receiver p 11161-036 12 89 12 3to 7 3to 7 891 0 ack from slave receiver ack from slave receiver sda scl s msb p 11161-037
ad9508 data sheet rev. g | page 32 of 40 figure 59. data transfer process (master read mode, two-byte transfer) data transfer format write byte format: the write byte protocol writes a register address to the ram, starting f rom the specified ram address. s slave address w a ram address high byte a ram address low byte a ram data 0 a ram data 1 a ram data 2 a p send byte format: the send byte protocol sets up the register address for subsequent reads. s slave address w a ram address high byte a ram address low byte a p receive byte format: the receive byte protocol reads the data byte(s) from ram, starting fr om the current address. s slave address r a ram data 0 a ram data 1 a ram data 2 a p read byte format: this is the combined format of the send byte and the receive byte. s slave address w a ram address high byte a ram address low byte a sr slave address r a ram data 0 a ram data 1 a ram data 2 a p i 2 c serial port timing figure 60. i 2 c serial port timing table 22. i 2 c timing definitions parameter description f scl serial clock t buf bus free time between stop and start conditions t hd; sta repeated hold time start condition t su; sta repeated start condition setup time t su; sto stop condition setup time t hd; dat data hold time t su; dat date setup time t low scl clock low period t high scl clock high period t r minimum/maximum receive scl and sda rise time t f minimum/maximum receive scl and sda fall time t sp pulse width of voltage spikes that must be suppressed by the input filter 12 89 12 3to 7 3to 7 891 0 ack from master receiver nack from master receiver sda scl s p 11161-039 ss r s p sda scl t sp t hd; sta t su; sta t su; dat t hd; dat t hd; sta t su; sto t buf t r t f t r t f t high t low 11161-038
data sheet ad9508 rev. g | page 33 of 40 register map register addresses that are not listed in table 23 are un used, and writing to those registers has no effect. the user shoul d write the default value to sections of registers marked reserved. the abbreviation, r, in the optional ( opt ) column in table 23 means read only and ns means that the value does not change during a soft reset. note that the default column is rep resented by def. table 23 . register map reg addr (hex) opt name d7 d6 d5 d4 d3 d2 d1 d0 def serial control port configuration and part identification 0x00 ns spi control sdo enable lsb first/ increment address soft reset reserved soft reset lsb first/ increment address sdo enable 00 0x00 ns i 2 c control reserved soft reset reserved soft reset reserved 00 0x0a r, ns silicon rev silicon r evision[7:0] 00 0x0b r, ns reserved reserved 00 0x0c r, ns part id clock part family id[7:0] 05 0x0d r,ns part id clock part family id[15:8] 00 chip level functions 0x12 reserved reserved 02 0x13 sleep reserved sleep reserved 00 0x14 ns sync_ bar reserved sync_ bar 01 out0 functions 0x15 out0 divide ratio [9:0] out0 divide ratio[7:0] 00 0x16 reserved out0 divide ratio[9:8] 00 0x17 out0 phase [9:0] out0 phase [7:0] 00 0x18 reserved out0 phase [10:8] 00 0x19 out0 driver pd_0 syncmask0 out0 driver phase [1:0] out0 mode [2:0] reserved 14 0x1a out0 cmos en_cmos_0p cmos_0p_ phase [1:0] en_cmos_0n cmos_0n_ phase [1:0] reserved 00 out1 fu nctions 0x1b out1 divide ratio [9:0] out1 divide ratio[7:0] 00 0x1c reserved out1 divide ratio[9:8] 00 0x1d out1 phase [9:0] out1 phase [7:0] 00 0x1e reserved out1 phase [10:8] 00 0x1f out1 driver pd_1 s yncmask 1 out1 driver phase [1:0] out1 mode [2:0] reserved 14 0x20 out1 cmos en_cmos_1p cmos_1p_phase [1:0] en_cmos_1n cmos_1n_phase [1:0] reserved 00 out2 fu nctions 0x21 out2 divide ratio [9:0] out2 divide ratio[7:0] 00 0x22 reserved out2 divide ratio[9:8] 00 0x23 out2 phase [9:0] out2 phase [7:0] 00 0x24 reserved out2 phase [10:8] 00 0x25 out2 driver pd_2 syncmask 2 out2 driver phase [1:0] out2 m ode [2:0] reserved 14 0x26 out2 cmos en_cmos_2p cmos_2p_phase [1:0] en_cmos_2n cmos_2n_phase [1:0] reserved 00 out3 fu nctions 0x27 out3 divide ratio [9:0] out3 divide ratio[7:0] 00 0x28 reserved out3 divide ratio[9:8] 00 0x29 out3 phase[9:0] out3 phase [7:0] 00 0x2a reserved out3 phase [10:8] 00 0x2b out3 driver pd_3 syncmask3 out3 driver phase [1:0] out3 mode [2:0] reserved 14 0x2c out3 cmos en_cmos_3p cmos_3p_phase [1:0] en_cmos_3n cmos_3n_phase [1:0] reserved 00
ad9508 data sheet rev. g | page 34 of 40 registe r map bit descriptio ns serial port configur ation (register 0 x 00) table 24 . serial configuration address bits bit name description 0x00 7 sdo enable enables spi port sdo pin. this bit does nothing in i 2 c mode. 1 = 4 - wire (sdo pin enabled). 0 = 3 - wire (default). 6 lsb first/increment address bit order for the spi port. this bit is nonfunctional in i 2 c mode. 1 = lsb and byte first. register addresses are automatically incremented in multibyte transfers. 0 = msb and byte first (default). register addresses are automatically decremented in multibyte transfers. 5 soft reset device reset . [4:3] reserved reserved. 2 soft reset same function as bit 5 of this register , set bit 2 and bit 5 to the same value. 1 lsb first/increment address same function as bit 6 of this register , set bit 1 and bit 6 to the same value . 0 sdo enable same function as bit 7 of this register , set bit 7 and bit 0 to the same value. silicon revision (re gister 0 x 0a to register 0 x 0d) table 25 . silicon revision address bits bit name description 0x0a [7:0] silicon r evision [7:0] a read - only register . identifies the revision level of the ad9508 . 0x0b [7:0] reserved 0x00 = default. 0x0c [7:0] clock part family id[7:0] a read - only register . this register, together with register 0x000d , uniquely identifies an ad9508 . no other device in the analog devices, inc., ad95xx family has a value of 0x0005 in these two registers. 0x05 = default . 0x0d [7:0] clock part family id[15:8] this register is a continuation of register 0x000c. 0x00 = default. chip level functions (reg ister 0 x12 to register 0 x14 ) table 26 . sleep and synchronization address bits bit name description 0x12 [7: 0] reserved 0x00000010 = default 0x13 [7:5] reserved 0x000 = default 4 sleep 0 = disables sleep mode (default) 1 = enables sleep mode [3:0] reserved 0x0000 = default 0x14 [7:1] reserved 0x0000000 = default 0 sync_bar 0 = enables a software output synchronization routine 1 = output synchronization via software disabled (default)
data sheet ad9508 rev. g | page 35 of 40 out0 functions (register 0x15 to register 0x1a) table 27. divide ratio and phase address bits bit name description 0x15 [7:0] out0 divide ratio[7:0] out0 10-bit divider value, bits[7:0] (lsb). bits[9:8] (msb) reside in register 0x16. division = out0 divide ratio, bits[9:0] + 1. for example, [9:0] = 0 is divide by 1, [9:0] = 1 is divide by 2 [9:0] = 1023 is divide by 1024. 0x16 [7:2] reserved 0x00 = default [1:0] out0 divide ratio[9:8] out0 10-bit divider value, bits[9:8] (msb). bits[7:0] (lsb) reside in register 0x15. division = out0 divide ratio, bits[9:0] + 1. for example, [9:0] = 0 is divide by 1, [9:0] = 1 is divide by 2 [9:0] = 1023 is divide by 1024. 0x17 [7:0] out0 phase[7:0] out0 11-bit phase offset value, bits[7:0] (lsb). bits[10:8] (msb) reside in register 0x18. phase offset = out0 phase, bits[10:0]. for example, [10:0] = 1 is the minimum phase offset of ? the input clock period, [10:0] = 2 is a phase offset of one input clock period. [10:0] = 2047 is a phase offset 2047 times ? the input clock period. 0x18 [7:3] reserved 0x00 = default [2:0] out0 phase[10:8] out0 11-bit phase offset value, bits[10:8] (msb). bits[7:0] (lsb) reside in register 0x17. phase offset = out0 phase, bits[10:0]. for example, [10:0] = 1 is the minimum phase offset of ? the input clock period, [10:0] = 2 is a phase offset of one input clock period. [10:0] = 2047 is a phase offset 2047 times ? the input clock period. table 28. output driver, power down, and sync address bits bit name description 0x19 7 pd_0 divider 0 power down 6 syncmask0 setting this bit masks divider 0 from the output sync function 0 = divider 0 is synchronized during output sync (default) 1 = divider 0 is excluded from an output sync [5:4] out0 driver phase[1:0] these bits determine the phase of the out0 driver 00 = force high 01 = noninverting (default) 10 = inverting 11 = force low [3:1] out0 mode[2:0] these bits determine the out0 driver mode 000 = lvds 0.5 3.5 ma (1/2 amplitude) 001 = lvds 0.75 3.5 ma (3/4 amplitude) 010 = lvds 1 3.5 ma (default) 011 = lvds 1.25 3.5 ma (1.25 amplitude) 100 = hstl 1 8 ma (normal amplitude) 101 = hstl boost mode (lvpecl compatible, 40 % additional amplitude), approximately 11 ma. 110 = high-z/cmos 111 = high-z/cmos 0 reserved 0b = default 0x1a 7 en_cmos_0p setting this bit enables the out0p cmos driver 0 = disables the out0p cmos driver (default) 1 = enables the out0p cmos driver [6:5] cmos_0p_phase[1:0] these bits determine the phase of the out0p cmos driver 00 = force high (default) 01 = noninverting 10 = inverting 11 = force low 4 en_cmos_0n setting this bit enables the out0n cmos driver 0 = disables the out0n cmos driver (default) 1 = enables the out0n cmos driver
ad9508 data sheet rev. g | page 36 of 40 address bits bit name description [3:2] cmos_0n_phase[1:0] these bits determine the phase of the out0n cmos driver 00 = force high (default) 01 = noninverting 10 = inverting 11 = force low [1:0] reserved 00b = default out1 functions (regi ster 0 x1b to register 0 x20 ) table 29 . divide ratio and phase address bits bit name description 0x1b [7:0] out1 divide ratio[7:0] out 1 10 - bit divider value, bits[7:0] (lsb). bits[9 : 8] (msb) reside in r egister 0x1c . division = out1 divide ratio , bits[9:0] + 1. for example, [9:0] = 0 is divide by 1, [9:0] = 1 is divide by 2 ? [9:0] = 1023 is divide by 1024. 0x1c [7:2] reserved 0x00 = default [1:0] out1 divide ratio[9:8] out1 10 - bit divider value, bits[9:8] (msb). bits[7:0] (lsb) reside in register 0x1b . division = out1 divide ratio , bits[9:0] + 1. for example, [9:0] = 0 is divide by 1, [9:0] = 1 is divide by 2 ? [9:0] = 1023 is divide by 1024. 0x1d [7:0] out1 phase[7:0] out 1 11 - bit phase offset value, bits[7:0] (lsb). bits[10: 8] (msb) reside in r egister 0x1e. phase offset = out1 phase , bits[10:0] . for example, [10:0] = 1 is the minimum phase offset of ? the input clock period, [10:0] = 2 is a phase offset of one input c lock period.? [10:0] = 2047 is a phase offset 2047 times ? the input clock period. 0x1e [7: 3] reserved 0x00 = default [2 :0] out1 phase[10:8] out 1 11 - bit phase offset value, bits[10:8] (msb). bits [7: 0] (lsb) reside in r egister 0x1d . phase offset = out1 phase , bits[10:0] . for example, [10:0] = 1 is the minimum phase offset of ? the input clock period, [10:0] = 2 is a phase offset of one input c lock period.? [10:0] = 2047 is a phase offset 2047 times ? the input clock period. table 30 . output driver, power down, and sync address bits bit name description 0x1f 7 pd_1 divider 1 power - down 6 syncmask1 setting this bit masks divider 1 from the output sync function 0 = divider 1 is synchronize d during output sync (default) 1 = divider 1 is excluded from an output sync [5:4] out1 driver phase [1:0] these bits determine the phase of the out1 driver 00 = force high 01 = non invert ing (default) 10 = inverting 11 = force low [3:1] out1 mode[2:0] these bits determine the out1 driver mode 000 = lvds 0.5 3.5 ma (1/2 amplitude) 001 = lvds 0.75 3.5 ma (3/4 amplitude) 010 = lvds 1 3.5 ma (default) 011 = lvds 1.25 3.5 ma (1.25 amplitude) 100 = hstl 1 8 ma (normal amplitude) 101 = hstl boost mode (lv pecl compatible, 40% additional amplitude), approximately 11 ma. 110 = high - z/cmos 111 = high - z/cmos 0 reserved 0b = default
data sheet ad9508 rev. g | page 37 of 40 address bits bit name description 0x20 7 en_cmos_1p setting this bit enables the out1p cmos driver 0 = disables the out1p cmos driver (default) 1 = enables the out1p cmos driver [6:5] cmos_1p_p hase [1:0] these bits determine the phase of the out1p cmos driver 00 = force high (default) 01 = noninvert ing 10 = invert ing 11 = force low [4] en_cmos_1n setting this bi t enables the out1n cmos driver 0 = disables the out1n cmos driver (default) 1 = enables the out1n cmos driver [3:2] cmos_1n_ phase [1:0] these bits determine the phase of the out1n cmos driver 00 = force high (default) 01 = noninvert ing 10 = i nvert ing 11 = force low [1:0] reserved 00b = default out2 functions (register 0 x21 to register 0 x26 ) table 31 . divide ratio and phase address bits bit name description 0x2 1 [7:0] out2 divide ratio[7:0] out 2 10 - bit divider value, bits[7:0] (lsb). bits[9: 8] (msb) reside in r egister 0x22 . division = out2 divide ratio , bits[9:0] + 1. for example, [9:0] = 0 is divide by 1, [9:0] = 1 is divide by 2 ? [9:0] = 1023 is divide by 1024. 0x2 2 [7:2] reserved 0x00 = default [1:0] out2 divide ratio[9:8] out2 10 - bit divider value, bits[9:8] (msb ). bits[ 7:0 ] ( lsb) reside in register 0x21 . division = out2 divide ratio , bits[9:0] + 1. for example, [9:0] = 0 is divide by 1, [9:0] = 1 is divide by 2 ? [9:0] = 1023 is divide by 1024. 0x23 [7:0] out2 phase[7:0] out 2 11 - bit phase offset value, bits[7:0] (lsb). bit s[10: 8] (msb) reside in r egister 0x24 . phase offset = out2 phase , bits[10 :0] . for example, [10:0] = 1 is the minimum phase offset of ? the input clock period, [10:0] = 2 is a phase offset of one input clock period. ? [10:0] = 2047 is a phase offset 2047 times ? the input clock period. 0x24 [7: 3] reserved 0x00 = default [2 :0] out2 phase[10:8] out2 11 - bit phase offset value, bits[10:8] (msb). bits [7: 0] (lsb) reside in r egister 0x23 . phase offset = out2 phase , bi ts[10:0] . for example, [10:0] = 1 is the minimum phase offset of ? the input clock period, [10:0] = 2 is a phase offset of one input c lock period.? [10:0] = 2047 is a phase offset 2047 times ? the input clock period. table 32 . output driver, power down, and sync address b its bit name description 0x25 7 pd_2 divider 2 power - down 6 syncmask2 setting this bit masks out2 from the output sync function 0 = divider 2 is synchronized during output sync (default) 1 = divider 2 is excluded from an output sync [5:4] out2 driver phase[1:0] these bits determine the phase of the out2 driver 00 = force high 01 = noninvert ing (default) 10 = invert ing 11 = force low
ad9508 data sheet rev. g | page 38 of 40 address b its bit name description [3:1] out2 mode[2:0] these bits determine the out2 driver mode 000 = lvds 0.5 3.5 ma (1/2 amplitude) 001 = lvds 0.75 3.5 ma (3/4 amplitude) 010 = lvds 1 3.5 ma (default) 011 = lvds 1.25 3.5 ma (1.25 amplitude) 100 = hstl 1 8 ma (normal amplitude) 101 = hstl boost mode (lv pecl compatible, 40% additional amplitude), approximately 11 ma. 110 = high - z/cmos 111 = high - z/cmos 0 reserved 0b = default 0x26 7 en_cmos_2p setting this bit enables the out2p cmos driver 0 = disables the out2p cmos driver (default) 1 = enables out2p cmos driver [6:5] cmos_2p_phase[1:0] these bits determine the phase of the out2p cmos driver 00 = force high (default) 01 = non inverting 10 = inverting 11 = force low 4 en_cmos_2n setting this bi t enables the out2n cmos driver 0 = disables the out2n cmos driver (default) 1 = enables out2n cmos driver [3:2] cmos_2n_phase[1:0] these bits determine the phase of the out2n cmos driver 00 = force high (default) 01 = non inverting 10 = inverting 11 = force low [1:0] reserved 00b = default out3 functions (regi ster 0 x27 to register 0 x2c ) table 33 . divide ratio and phase address bits bit name description 0x27 [7:0] out3 divide ratio[7:0] out3 10 - bit divider value, bits[7:0] (lsb). bits[9: 8] (msb) reside in r egister 0x28 . division = out3 divide ratio , bits[9:0] + 1. for example, [9:0] = 0 is divide by 1, [9:0] = 1 is divide by 2 ? [9:0] = 1023 is divide by 1024. 0x28 [7:2] reserved 0x00 = default [1:0] out3 divide ratio[9:8] out 3 10 - bit divider value, bits[9:8] (msb). bits[7:0] (lsb) reside in register 0x27 . division = out3 divide ratio , bits[9:0] + 1. for example, [9:0] = 0 is divide by 1, [9:0] = 1 is divide by 2 ? [9:0] = 1023 is divide by 1024. 0x29 [7:0] out3 phase[7:0] out 3 11 - bit phase offset value, b its[7:0] (lsb). bits[10: 8] (msb) reside in r egister 0x2a . phase offset = out3 phase , bits[10:0]. for example, [10:0] = 1 is the minimum phase offset of ? the input clock period, [10:0] = 2 is a phase offset of one input c lock period.? [10:0] = 2047 is a phase offset 2047 times ? the input clock period 0x2a [7: 3] reserved 0x00 = default [2 :0] out3 phase[10:8] out3 11 - bit phase offset value, bits[10:8] (msb). bits[7 : 0] (lsb) reside in r egister 0x29 . phase offset = out3 phase , bits[10:0] . for example, [10:0] = 1 is the minimum phase offset of ? the input clock period, [10:0] = 2 is a phase offset of one input c lock period.? [10:0] = 2047 is a phase offset 2047 times ? the input clock period.
data sheet ad9508 rev. g | page 39 of 40 table 34 . output driver, power down, and sync address bits bit name description 0x2b 7 pd_3 divider 3 power - down 6 syncmask3 setting this bit masks out3 from the output sync function 0 = divider 3 is synchronized during output sync (default) 1 = divider 3 is excluded from an output sync [5:4] out3 driver phase[1:0] these bits determine the phase of the out3 driver 00 = force high 01 = non inverting 10 = inverting 11 = force low [3:1] out3 mode[2:0] these bits determine the out3 driver mode 000 = lvds 0.5 3.5 ma (1/2 amplitude) 001 = lvds 0.75 3.5 ma (3/4 amplitude) 010 = lvds 1 3.5 ma (default) 011 = lvds 1.25 3.5 ma (1.25 amplitude) 100 = hstl 1 8 ma (normal amplitude) 101 = hstl boost mode (lv pecl compatible, 40% additional amplitude), approximately 11 ma. 110 = high - z/cmos 111 = high - z/cmos 0 reserved 0b = default 0x2c 7 en_cmos_3p setting this bit enables the out3p cmos driver 0 = disables the out3p cmos driver (default) 1 = enables out3p cmos driver [6:5] cmos_3p_phase[1:0] these bits determine the phase of the out3p cmos driver 00 = force high (default) 01 = non inverting 10 = inverting 11 = force low 4 en_cmos_3n setting this bi t enables the out3n cmos driver 0 = disables the out3n cmos driver (default) 1 = enables out3n cmos driver [3:2] cmos_3n_phase[1:0] these bits determine the phase of the out3n cmos driver 00 = force high (default) 01 = non inverting 10 = inverting 11 = force low [1:0] reserved 00b = default
ad9508 data sheet rev. g | page 40 of 40 packaging and ordering information outline dimensions figure 61 . 24 - lead lead frame chip scale package [lfcsp ] 4 mm 4 mm body and 0.75 mm package height (cp - 24 - 14 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9508bcpz ?40c to +85c 24 - lead lead frame chip scale package [ lfcsp ] cp - 24 - 14 ad9508bcpz - reel7 ?40c to +85c 24 - lead lead frame chip scale package [ lfcsp ] cp - 24 - 14 ad9508/pcbz evaluation board 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by phil ips semiconductors (now nxp semiconductors). 0.80 0.75 0.70 pkg-003994/5 11 1 0.50 bsc 0.50 0.40 0.30 compliant to jedec standards mo-220-wggd-8 bot t om view top view 4.10 4.00 sq 3.90 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 pin 1 indic at or 1 24 7 12 13 18 19 6 03-09-2017-b 0.30 0.25 0.20 0.20 min 2.44 2.30 sq 2.16 exposed pad sea ting plane pin 1 indic at or area options (see detail a) detail a (jedec 95) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. ? 2013 ? 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11161 -0- 6/17(g)

▲Up To Search▲

Price & Availability of AD9508-17

	To Download AD9508-17 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .